The present invention relates to a method for manufacturing a semiconductor integrated circuit in which the packaging density is high and high speed operation is possible.
In the manufacture of integrated circuits, the quality of integrated circuits is being improved by reducing the parasitic capacity, raising the packaging density or forming a suitable impurity profile. For example, it is known that the adoption of the oxidation film isolating technique can reduce the parasitic capacity of the base region and the epitaxial layer, and as compared with the p-n isolation technique, the insulating distance between the transistors may be reduced and the surface of the integrated circuit element may be flattened. It is also known to use polycrystalline silicon doped with an impurity as a diffusion source to form a shallow diffusion layer in a well controlled manner, and to use the polycrystalline silicon as electrode wiring.
A manufacturing method for a conventional bipolar integrated circuit utilizing such techniques will be described taking an Integrated Injection Logic (to be referred to as an I.sup.2 L for brevity hereinafter) as an example. An n.sup.+ -type buried layer is formed in a p-type silicon substrate and an n-type epitaxial layer is grown thereover. A thick isolating oxidation film is formed between the elements by the oxidation film isolation technique. Boron, which is a p-type impurity, is selectively ion-implanted to form a p.sup.+ -type injector and a base region. A silicon oxide film is formed on the entire surface of the substrate. A collector impurity diffusion window is formed by etching the oxidation film. A polycrystalline silicon film doped with arsenic, which is an n-type impurity, is deposited on the oxidation film. Arsenic within the polycrystalline silicon film is by heat-treatment diffused into the base region to form n.sup.+ -type collector regions. The polycrystalline silicon film is selectively etched by photoengraving to form wiring for connecting with the collectors of polycrystalline silicon, and a low temperature oxidation film is deposited on the entire surface of the structure. Thereafter, contact holes for the injector and the base are formed in the silicon oxidation films. By evaporation of aluminum and patterning of the formed aluminum film, second layer wirings are formed connected with the injector and the base region through the contact holes to provide an I.sup.2 L circuit.
However, with such a conventional method, the arsenic doped polycrystalline silicon is deposited on the silicon oxidation film having a diffusion window, the collector regions are formed using this as a diffusion source, and the first layer wiring (the wiring for connecting the collectors) is formed by photoengraving. Accordingly, the first layer wiring connecting the collector regions necessarily becomes greater than the area of the collector regions. Further, since extra space is necessary for aligning the first layer wiring with the mask, the space between the plurality of collector regions necessarily becomes long. As a result, the packaging density of the I.sup.2 L circuit is extremely degraded, the area ratio of the collector regions to that of the base region (SC/SB) is decreased, and the current-amplification factor (.beta.up) is reduced, thereby obstructing high speed operation. Since the second layer wiring to the base region is performed through the contact hole, the resistances of the collector regions far from the base contact becomes greater, so that the base potential drops and the performance of the collectors far from the injector is degraded.